ATMEGA8U2_14 Datasheet, PDF (259/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
25.8
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using a serial programming
bus while RESET is pulled to GND. The serial programming interface consists of pins SCK, PDI
(input) and PDO (output). After RESET is set low, the Programming Enable instruction needs to
be executed first before program/erase operations can be executed. NOTE, in Table 25-14 on
page 259, the pin mapping for serial programming is listed. Not all packages use the SPI pins
dedicated for the internal Serial Peripheral Interface - SPI.
25.9 Serial Programming Pin Mapping
Table 25-14. Pin Mapping Serial Programming
Symbol
Pins
I/O
PDI
PB2
I
PDO
PB3
O
SCK
PB1
I
Figure 25-7. Serial Programming and Verify⁽¹⁾
Description
Serial Data in
Serial Data out
Serial Clock
PDI
PDO
SCK
XTAL1
+1.8 - 5.5V
VCC
+1.8 - 5.5V⁽²⁾
AVCC
RESET
GND
Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
XTAL1 pin.
2. V_CC - 0.3V < AVCC < V_CC + 0.3V, however, AVCC should always be within 1.8 - 5.5V
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f_ck < 12 MHz, 3 CPU clock cycles for f_ck >= 12 MHz
High: > 2 CPU clock cycles for f_ck < 12 MHz, 3 CPU clock cycles for f_ck >= 12 MHz
7799D–AVR–11/10
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