ATMEGA8U2_14 Datasheet, PDF (127/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Using the ICRn Register for defining TOP works well when using fixed TOP values. By using
ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However,
if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as
TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-
forms on the OCnx pins. Setting the COMnx[1:0] bits to two will produce a non-inverted PWM
and an inverted PWM output can be generated by setting the COMnx1:0 to three (See Table 16-
3 on page 131). The actual OCnx value will only be visible on the port pin if the data direction for
the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clear-
ing) the OCnx Register at the compare match between OCRnx and TCNTn when the counter
increments, and clearing (or setting) the OCnx Register at compare match between OCRnx and
TCNTn when the counter decrements. The PWM frequency for the output when using phase
and frequency correct PWM can be calculated by the following equation:
f _OCnxPFCPWM
=
-------^f---^c--^l-^k---^_--^I--^/-^O-------
2  N  TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A
is used to define the TOP value (WGM1[3:0] = 9) and COM1A[1:0] = 1, the OC1A output will tog-
gle with a 50% duty cycle.
16.10 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk_Tn) is therefore shown as a
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for
modes utilizing double buffering). Figure 16-10 shows a timing diagram for the setting of OCFnx.
Figure 16-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling
clk_I/O
clk_Tn
(clk_I/O/1)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 16-11 shows the same timing data, but with the prescaler enabled.
7799D–AVR–11/10
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