ATMEGA8U2_14 Datasheet, PDF (192/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
20.5.3
Freeze clock
The firmware has the ability to freeze the clock of USB controller by setting the FRZCLK bit, and
thereby reduce the power consumption. When FRZCLK is set, it is still possible to access to the
following registers:
• USBCON
• DPRAM direct access registers (DPADD7:0, UEDATX)
• UDCON
• UDINT
• UDIEN
When FRZCLK is set, only the asynchronous interrupt may be triggered:
• WAKEUPI
20.6 Memory management
The controller does only support the following memory allocation management.
The reservation of an Endpoint can only be made in the increasing order (Endpoint 0 to the last
Endpoint). The firmware shall thus configure them in the same order.
The reservation of an Endpoint kⁱ is done when its ALLOC bit is set. Then, the hardware allo-
cates the memory and insert it between the Endpoints k^i-1 and kⁱ⁺¹. The kⁱ⁺¹ Endpoint memory
“slides” up and its data is lost. Note that the kⁱ⁺² and upper Endpoint memory does not slide.
Clearing an Endpoint enable (EPEN) does not clear either its ALLOC bit, or its configuration
(EPSIZE/PSIZE, EPBK/PBK). To free its memory, the firmware should clear ALLOC. Then, the
kⁱ⁺¹ Endpoint memory automatically slides down. Note that the kⁱ⁺² and upper Endpoint memory
does not slide.
The following figure illustrates the allocation and reorganization of the USB memory in a typical
example:
Table 20-1. Allocation and reorganization USB memory flow
7799D–AVR–11/10
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