ATMEGA8U2_14 Datasheet, PDF (214/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
21.18.8 UENUM – USB Endpoint Number Register
Bit
7
6
5
4
3
2
1
0
(0xE9)
-
-
-
-
-
EPNUM[2:0]
UENUM
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bits 7:3 – Res: Reserved
These bits are reserved and will always read as zero.
• Bits 2:0 – EPNUM[2:0] Endpoint Number Bits
Writing these bits allows to select the hardware endpoint number that can be accessed by the
CPU interface. This register select the target endpoint number for UECONEX, UECFG0X,
UECFG1X, UESTA0X, UESTA1X, UEINTX, UEIENX, UEDATX, UEBCLX registers. See “End-
point selection” on page 198 for more details.
21.18.9 UERST – USB Endpoint Reset Register
Bit
7
6
5
4
3
2
1
0
(0xEA)
-
-
-
EPRST D4 EPRST D3 EPRST D2 EPRST D1 EPRST D0 UERST
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bits 7:5 – Res: Reserved
These bits are reserved and will always read as zero.
• Bits 4:0 – EPRST[4:0]: Endpoint FIFO Reset Bits
Writing this bit to one keeps the selected endpoint (UENUM register value) under reset state.
selected. Writing this bit to zero completes the endpoint reset operation and makes the endpoint
usable. See “Endpoint reset” on page 197 for more information.
21.18.10 UECONX – USB Endpoint Control Register
Bit
7
(0xEB)
-
Read/Write
R
Initial Value
0
6
5
4
3
2
-
STALLRQ STALLRQC RSTDT
-
R
R/W
R/W
R/W
R
0
0
0
0
0
1
0
-
EPEN
UECONX
R
R/W
0
0
• Bits 7:6 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 5 – STALLRQ: STALL Request Handshake Bit
Writing this bit to one allows the USB controller to generate a STALL answer for the next SETUP
transaction received. This bit is cleared by hardware when the STALL handshake is sent or
when a new SETUP token is received. Writing this bit to zero has no effect. The STALL hand-
shake can be abort using STALLRQC bit.
See “STALL request” on page 201 for more details.
7799D–AVR–11/10
214