ATMEGA8U2_14 Datasheet, PDF (198/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
• the Rx and Tx banks are cleared and their internal pointers are restored,
• the UEINTX, UESTA0X and UESTA1X are restored to their reset value.
The data toggle field remains unchanged.
The other registers remain unchanged.
The endpoint configuration remains active and the endpoint is still enabled.
The endpoint reset may be associated with a clear of the data toggle command (RSTDT bit) as
an answer to the CLEAR_FEATURE USB command.
21.4 USB reset
When an USB reset is detected on the USB line (SEO state with a minimal duration of 100μs),
the next operations are performed by the controller:
• All the endpoints are disabled.
• The default control endpoint remains configured.
• The data toggle of the default control endpoint is cleared.
If the hardware reset function is selected, a reset is generated to the CPU core without disabling
the USB controller (that remains in the same state than after a USB Reset).
21.5
Endpoint selection
Prior to any operation performed by the CPU, the endpoint must first be selected. This is done
by setting the EPNUM[2:0] bits (in UENUM register) with the endpoint number which will be
managed by the CPU.
The CPU can then access to the various endpoint registers and data.
21.6
Endpoint activation
The endpoint is maintained under reset as long as the EPEN bit is not set.
The following flow must be respected in order to activate an endpoint:
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