ATMEGA8U2_14 Datasheet, PDF (213/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
21.18.5 UDFNUMH – USB Device Frame Number High Register
Bit
7
6
5
4
3
2
1
0
(0xE5)
-
-
-
-
-
FNUM[10:8]
UDFNUMH
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
• Bits 7:3 – Res: Reserved
These bits are reserved and will always read as zero.
• Bits 2:0 – FNUM[10:8]: Frame Number Upper Flag
These bits are read-only and updated by the hardware USB controller. These bits contains the 3
MSB of the 11-bits Frame Number information. The content of these bits is updated with the last
received SOF packet. These bits are updated even if a corrupted SOF has been received. When
a corrupted SOF number is detected, the FNCERR bit of UDMFN is set.
21.18.6 UDFNUML – USB Device Frame Number Low Register
Bit
7
6
5
4
3
2
1
0
(0xE4)
FNUM[7:0]
UDFNUML
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
• Bits 7:0 – FNUM: Frame Number Lower Flag
These bits are read-only and updated by the hardware USB controller. These bits contains the 8
LSB of the 11-bits Frame Number information. The content of these bits is updated with the last
received SOF packet. These bits are updated even if a corrupted SOF has been received. When
a corrupted SOF number is detected, the FNCERR bit of UDMFN is set.
21.18.7 UDMFN – USB Device Micro Frame Number
Bit
7
6
5
4
3
2
1
0
(0xE6)
-
-
-
FNCERR
-
-
-
-
UDMFN
Read/Write
R
R
R
R/W
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
• Bit 7:5 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 4 – FNCERR: Frame Number CRC Error Flag
This bit is set by the USB controller when a corrupted frame number in Start of frame packet is
received. When an incorrect frame number is detected both SOFI flag and this bit are set.
• Bits 3:0 – Res: Reserved
These bits are reserved and will always read as zero.
7799D–AVR–11/10
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