ATMEGA8U2_14 Datasheet, PDF (62/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Table 10-8. Watchdog Timer Prescale Select, DIV = 5 (CLKwdt = CLK128 / 11)
WDP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
WDP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
WDP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
WDP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Number of WDT Oscillator
Cycles before 1st time-out
(Early warning)
2K (2048) cycles
4K (4096) cycles
8K (8192) cycles
16K (16384) cycles
32K (32768) cycles
64K (65536) cycles
128K (131072) cycles
256K (262144) cycles
512K (524288) cycles
1024K (1048576) cycles
Early warning Typical
Time-out at
V_CC = 5.0V
88 ms
176 ms
352 ms
704 ms
1.4 s
2.8 s
5.6 s
11.2 s
22.5 s
45s
Reserved
Watchdog
Reset/Interrupt Typical
Time-out at
V_CC = 5.0V
176 ms
352 ms
704 ms
1.4 s
2.8 s
5.6 s
11.2 s
22.5 s
45 s
90 s
Table 10-9. Watchdog Timer Prescale Select, DIV = 6(CLKwdt = CLK128 / 13)
WDP3
0
0
0
0
0
0
0
0
1
1
WDP2
0
0
0
0
1
1
1
1
0
0
WDP1
0
0
1
1
0
0
1
1
0
0
WDP0
0
1
0
1
0
1
0
1
0
1
Number of WDT Oscillator
Cycles before 1st time-out
(Early warning)
2K (2048) cycles
4K (4096) cycles
8K (8192) cycles
16K (16384) cycles
32K (32768) cycles
64K (65536) cycles
128K (131072) cycles
256K (262144) cycles
512K (524288) cycles
1024K (1048576) cycles
Early warning Typical
Time-out at
V_CC = 5.0V
104 ms
208 ms
416 ms
832 ms
1.6 s
3.3 s
6.6 s
13.3 s
26.6 s
53.2 s
Watchdog
Reset/Interrupt Typical
Time-out at
V_CC = 5.0V
208 ms
416 ms
832 ms
1.64 s
3.3 s
6.6 s
13.3 s
26.6 s
53.2 s
106.4 s
62
7799D–AVR–11/10