ATMEGA8U2_14 Datasheet, PDF (185/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
20. USB Controller
20.1 Features
• USB 2.0 Full-speed device
• Ping-pong mode (dual bank), with transparent switch
• 176 bytes of DPRAM
– 1 endpoint of 64 bytes max (default control endpoint)
– 2 endpoints of 64 bytes max (one bank)
– 2 endpoints of 64 bytes max (one or two banks)
20.2 Overview
The USB controller provides the hardware to implement a USB2.0 compliant Full-Speed USB
device in the ATmega8U2/16U2/32U2. A simplified block diagram of the USB controller is shown
in Figure 20-1 on page 185.
The USB controller requires a 48 MHz ±0.25% reference clock for USB Full-Speed compliance.
This clock is generated by an internal PLL. The reference clock to the PLL must be provided
from an external crystal or an external clock input. Only these two clock options will be able to
provide a reference clock within the accuracy and jitter requirements of the USB specification.
See section “System Clock and Clock Options” on page 26 for details on the
ATmega8U2/16U2/32U2 system clock and clock options.
To comply to the USB specifications electrical characteristics, the USB Pads (D+ or D-) must be
powered at 3.0V to 3.6V. As the ATmega8U2/16U2/32U2 can be powered up to 5.5V, an inter-
nal regulator is provided to correctly power the USB pads. See “USB Module Powering Options”
on page 186 for details on the powering options available for the USB controller
Figure 20-1. USB controller Block Diagram
UVCC
XTAL1
Regulator
UCAP
D-
D+
clk
PLL
8MHz
6x
clk
48MHz
PLL clock
Prescaler
DPLL
Clock
Recovery
USB
Interface
CPU
On-Chip
USB DPRAM
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