ATMEGA8U2_14 Datasheet, PDF (26/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
8. System Clock and Clock Options
8.1 Clock Systems and their Distribution
Figure 8-1 presents the principal clock systems in the AVR and their distribution. All of the clocks
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in “Power Manage-
ment and Sleep Modes” on page 42. The clock systems are detailed below.
Figure 8-1. Clock Distribution
USB
General I/O
Modules
CPU Core
RAM
Flash and
EEPROM
clk_{USB (48MHz)}
USB PLL
X6
clk_{Pllin (8MHz)}
PLL Clock
Prescaler
clk_{XTAL (2-16 MHz)}
clk_I/O
AVR Clock
Control Unit
clk_CPU
clk_FLASH
Reset Logic
Watchdog Timer
Source clock
System Clock
Prescaler
Clock
Multiplexer
Watchdog clock
Watchdog
Oscillator
8.1.1
8.1.2
8.1.3
Crystal
Oscillator
External
Clock
Calibrated RC
Oscillator
CPU Clock – clk_CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
I/O Clock – clk_I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted.
Flash Clock – clk_FLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
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