ATMEGA8U2_14 Datasheet, PDF (208/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
21.17 Interrupts
It is not possible to have overflow error during IN stage, in the CPU side, since the CPU should
write only if the bank is ready to access data (TXINI=1 or RWAL=1).
The next figure shows all the interrupts sources:
Figure 21-4. USB Device Controller Interrupt System
UPRSMI
UDINT.6
EORSMI
UDINT.5
WAKEUPI
UDINT.4
EORSTI
UDINT.3
SOFI
UDINT.2
SUSPI
UDINT.0
UPRSME
UDIEN.6
EORSME
UDIEN.5
WAKEUPE
UDIEN.4
EORSTE
UDIEN.3
SOFE
UDIEN.2
SUSPE
UDIEN.0
USB Device
Interrupt
There are 2 kind of interrupts: processing (i.e. their generation are part of the normal processing)
and exception (errors).
Processing interrupts are generated when:
• Upstream resume(UPRSMI)
• End of resume(EORSMI)
• Wake up(WAKEUPI)
• End of reset (Speed Initialization)(EORSTI)
• Start of frame(SOFI, if FNCERR=0)
• Suspend detected after 3 ms of inactivity(SUSPI)
Exception Interrupts are generated when:
• CRC error in frame number of SOF(SOFI, FNCERR=1)
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