ATMEGA8U2_14 Datasheet, PDF (109/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Figure 16-1. 16-bit Timer/Counter Block Diagram⁽¹⁾
Count
Clear
Direction
Control Logic
TCLK
Timer/Counter
TCNTn
TOP BOTTOM
=
=0
=
OCRnA
=
OCRnB
Fixed
TOP
Values
=
OCRnC
ICRn
TCCRnA
ICFn (Int.Req.)
Edge
Detector
TCCRnB
TOVn
(Int.Req.)
Clock Select
Edge
Detector
( From Prescaler )
OCFnA
(Int.Req.)
Waveform
Generation
Tn
OCnA
OCFnB
(Int.Req.)
Waveform
Generation
OCnB
OCFnC
(Int.Req.)
Waveform
Generation
OCnC
( From Analog
Comparator Ouput )
Noise
Canceler
TCCRnC
ICPn
16.2.1 Registers
Note: 1. Refer to Figure 1-1 on page 2, Table 12-3 on page 74, and Table 12-6 on page 77 for
Timer/Counter1 pin placement and description.
The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg-
ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-
bit registers. These procedures are described in the section “Accessing 16-bit Registers” on
page 110. The Timer/Counter Control Registers (TCCRnA/B/C) are 8-bit registers and have no
CPU access restrictions. Interrupt requests (shorten as Int.Req.) signals are all visible in the
Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer Inter-
rupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure since these
registers are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the clock select logic is referred to as the timer clock (clk_Tn).
The double buffered Output Compare Registers (OCRnA/B/C) are compared with the
Timer/Counter value at all time. The result of the compare can be used by the Waveform Gener-
ator to generate a PWM or variable frequency output on the Output Compare pin (OCnA/B/C).
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