ATMEGA8U2_14 Datasheet, PDF (218/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
• Bit 1:0 – NBUSYBK[1:0]: Busy Bank Flag
These flags are set by hardware to indicate the number of busy bank for the selected endpoint
as shown in Table 21-6.
For IN endpoint, it indicates the number of busy bank(s), filled by the user, ready for IN transfer.
For OUT endpoint, it indicates the number of busy bank(s) filled by OUT transaction from the
host.
Table 21-6. NBUSYBK[1:0] Bits Settings
NBUSYBK1
NBUSYBK0
0
0
0
1
1
0
1
1
Number of busy banks
All banks are free
1 busy bank
2 busy banks
Reserved
21.18.14 UESTA1X – USB Endpoint Status 1 Register
Bit
7
6
5
4
3
2
1
0
(0xEF)
-
-
-
-
-
CTRLDIR
CURRBK[1:0]
UESTA1X
Read/Write
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
• Bits 7:3 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 2 – CTRLDIR: Control Direction
This flag is updated by the USB controller when a SETUP packet has been received. This flag
bit can be used for debug purpose to give the direction of the following packet. Reading one
from this flag means that the following packet is for an IN request, reading zero for an OUT
request.
• Bits 1:0 – CURRBK[1:0]: Current Bank
These flags are set by hardware to indicate the current bank number in used with the selected
endpoint as shown in Table 21-6. These flags are not relevant for control endpoint (control end-
point can not be configured in dual bank mode).These flags can be used for debug purpose and
are optional for data transfer with endpoint in dual bank mode.
Table 21-7. CURRBK[1:0] Bits Settings
CURRBK1
CURRBK0
0
0
0
1
1
0
1
1
Current Bank Number
Bank 0
Bank 1
Reserved
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