ATMEGA8U2_14 Datasheet, PDF (17/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Figure 7-1. Program Memory Map
Program Memory
0x00000
Application Flash Section
Boot Flash Section
0x7FFF (32KBytes)
0x3FFF (16KBytes)
0x1FFF (8KBytes)
7.2 SRAM Data Memory
Figure 7-2 shows how the ATmega8U2/16U2/32U2 SRAM Memory is organized.
The ATmega8U2/16U2/32U2 is a complex microcontroller with more peripheral units than can
be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For
the Extended I/O space from $060 - $0FF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
The first 768 Data Memory locations address the Register File, the I/O Memory, Extended I/O
Memory, and the internal data SRAM. The first 32 locations address the Register file, the next
64 location the standard I/O Memory, then 160 locations of Extended I/O memory, and the 512
locations of internal data SRAM.The five different addressing modes for the data memory cover:
Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-
increment. In the Register file, registers R26 to R31 feature the indirect addressing pointer
registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
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