ATMEGA8U2_14 Datasheet, PDF (271/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

7799D–AVR–11/10
ATmega8U2/16U2/32U2
Figure 26-6. Parallel Programming Timing, Loading Sequence with Timing Requirements⁽¹⁾
XTAL1
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
t _XLXH
LOAD DATA LOAD DATA
(HIGH BYTE)
t_XLPH
t_PLXH
LOAD ADDRESS
(LOW BYTE)
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note: 1. The timing requirements shown in Figure 26-5 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply to load-
ing operation.
Figure 26-7. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Timing Requirements⁽¹⁾
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
XTAL1
t_XLOL
t_BVDV
BS1
OE
t_OLDV
t_OHDZ
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note: 1. The timing requirements shown in Figure 26-5 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply to read-
ing operation.
Table 26-9. Parallel Programming Characteristics, V_CC = 5V ± 10%
Symbol
Parameter
Min Typ Max Units
V_PP
I_PP
t_DVXH
t_XLXH
t_XHXL
t_XLDX
Programming Enable Voltage
Programming Enable Current
Data and Control Valid before XTAL1 High
XTAL1 Low to XTAL1 High
XTAL1 Pulse Width High
Data and Control Hold after XTAL1 Low
11.5
12.5
V
250
A
67
ns
200
ns
150
ns
67
ns
271