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ATMEGA8U2_14 Datasheet, PDF (246/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution
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ATmega8U2/16U2/32U2
25. Memory Programming
25.1
Program And Data Memory Lock Bits
The ATmega8U2/16U2/32U2 provides six Lock bits which can be left unprogrammed (“1”) or
can be programmed (“0”) to obtain the additional features listed in Table 25-2. The Lock bits can
only be erased to “1” with the Chip Erase command.
Table 25-1. Lock Bit Byte(1)
Lock Bit Byte
Bit No
7
6
BLB12
5
BLB11
4
BLB02
3
BLB01
2
LB2
1
LB1
0
Description
–
–
Boot Lock bit
Boot Lock bit
Boot Lock bit
Boot Lock bit
Lock bit
Lock bit
Default Value
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
0 (programmed)
1 (unprogrammed)
1 (unprogrammed)
0 (programmed)
0 (programmed)
Note: 1. “1” means unprogrammed, “0” means programmed
Table 25-2. Lock Bit Protection Modes(1)(2)
Memory Lock Bits
Protection Type
LB Mode
LB2
LB1
1
1
1
No memory lock features enabled.
Further programming of the Flash and EEPROM is disabled in
2
1
0
Parallel and Serial Programming mode. The Fuse bits are
locked in both Serial and Parallel Programming mode.(1)
Further programming and verification of the Flash and
3
0
0
EEPROM is disabled in Parallel and Serial Programming mode.
The Boot Lock bits and Fuse bits are locked in both Serial and
Parallel Programming mode.(1)
BLB0 Mode BLB02 BLB01
1
1
1
No restrictions for SPM or (E)LPM accessing the Application
section.
2
1
0
SPM is not allowed to write to the Application section.
SPM is not allowed to write to the Application section, and
(E)LPM executing from the Boot Loader section is not allowed
3
0
0
to read from the Application section. If Interrupt Vectors are
placed in the Boot Loader section, interrupts are disabled while
executing from the Application section.
(E)LPM executing from the Boot Loader section is not allowed
4
0
1
to read from the Application section. If Interrupt Vectors are
placed in the Boot Loader section, interrupts are disabled while
executing from the Application section.
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