C509-L_97 Datasheet, PDF (98/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
6.2.1 Timer/Counter 0 / 1 Registers
The Timer 0/1 unit of the C509-L is controlled by totally 8 special function registers: TCON, TMOD,
PRSC, IEN0, TL0, TH0, TL1, and TH1.
Each timer consists of two 8-bit registers (TH0 and TL0 for timer/counter 0, TH1 and TL1 for
timer/counter 1) which may be combined to one timer configuration depending on the mode that is
established. The functions of the timers are controlled by two special function registers TCON and
TMOD. The interrupt enable control bits are located in the SFR IEN0.
The upper four bits of the special function register TCON are the run and overflow flags for timer 0
and 1.
Special Function Register TCON (Address. 88H)
Special Function Register IEN0 (Address. A8H)
Reset Value : 00H
Reset Value : 00H
MSB
Bit No. 8F_H
8E_H 8D_H
8C_H
8B_H 8A_H
LSB
89_H 88_H
88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TCON
A8H
AF_H AE_H
EAL WDT
AD_H
ET2
AC_H AB_H AA_H
ES0 ET1 EX1
A9_H
ET0
A8_H
EX0
IEN0
The shaded bits are not used for timer/counter 0 and 1.
Bit
Function
TF1
Timer 1 overflow flag
Set by hardware on timer/counter 1 overflow. Cleared by hardware when
processor vectors to interrupt routine.
TR1
Timer 1 run control bit.
Set/cleared by software to turn timer/counter 1 on/off.
TF0
Timer 0 overflow flag
Set by hardware on timer/counter 0 overflow. Cleared by hardware when
processor vectors to interrupt routine.
TR0
Timer 0 run control bit.
Set/cleared by software to turn timer/counter 0 on/off.
ET1
Timer 1 overflow interrupt enable.
If ET1 = 0, the timer 1 interrupt is disabled.
ET0
Timer 0 overflow interrupt enable.
If ET0 = 0, the timer 0 interrupt is disabled.
Semiconductor Group
6-20
1997-10-01