C509-L_97 Datasheet, PDF (77/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Reset / System Clock
C509-L
5.6 System Clock Output
For peripheral devices requiring a system clock, the C509-L provides a clock output signal derived
from the oscillator frequency as an alternate output function on pin P1.6/CLKOUT. lf bit CLK is set
(bit 6 of special function register ADCON0), a clock signal with 1/6 or 1/12 of the oscillator frequency
(depending on bit CLKP in SFR SYSCON) is gated to pin P1.6/CLKOUT. To use this function the
port pin must be programmed to a one (1), which is also the default after reset.
Special Function Register ADCON0 (Address D8H)
Special Function Register SYSCON (Address B1H)
Reset Value : 00H
Reset Value : 1010XX01B
Bit No.
D8H
B1H
MSB
DFH
BD
DEH DDH DCH DBH DAH D9H
CLK ADEX BSY ADM MX2 MX1
LSB
D8H
MX0
ADCON0
7
6
5
4
3
CLKP PMOD EALE RMAP –
2
1
0
– XMAP1 XMAP0 SYSCON
These bits are not used in controlling the clock output function.
Bit
CLK
CLKP
Function
Clock output enable bit
When set, pin P1.6/CLKOUT outputs the system clock which is 1/6 or 1/12 of
the oscillator frequency.
Prescaler control for the clock output signal CLKOUT
CLKP = 0 : CLKOUT frequency is f_OSC/6
CLKP = 1 : CLKOUT frequency is f_OSC/12 (default after reset)
A timing diagram of the system clock output is shown in figure 5-7. This timing assumes that CLK=1
and CLKP=0.
Note : During slow-down operation the frequency of the CLKOUT signal is further divided by eight.
Semiconductor Group
5-8
1997-10-01