C509-L_97 Datasheet, PDF (278/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Device Specifications
C509-L
External Data Memory Characteristics
Parameter
RD pulse width
WR pulse width
Address hold after ALE
RD to valid data in
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR or RD
Address valid to WR
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD
Symbol
Limit Values
Unit
16-MHz clock
Duty Cycle
0.45 to 0.55
Variable Clock
1/CLP= 3.5 MHz to
16 MHz
min. max. min.
max.
t_RLRH
t_WLWH
t_LLAX2
t_RLDV
t_RHDX
t_RHDZ
t_LLDV
t_AVDV
t_LLWL
t_AVWL
t_WHLH
t_QVWX
t_QVWH
t_WHQX
t_RLAZ
158 –
3 CLP-30 –
ns
158 –
3 CLP-30 –
ns
48 –
CLP -15 –
ns
–
100 –
0
0
2 CLP+
ns
TCL_Hmin-50
–
ns
–
51 –
CLP-12
ns
–
200 –
4 CLP-50 ns
–
200 –
4 CLP+
ns
TCL_Hmin-75
73 103 CLP+
CLP+
ns
TCL_Lmin-15 TCL_Lmin+15
95 –
2 CLP-30 –
ns
10 40
5
–
163 –
5
–
–
0
TCL_Hmin-15
TCL_Lmin-20
3 CLP+
TCL_Lmin-50
TCL_Hmin-20
–
TCL_Hmin+15 ns
–
ns
–
ns
–
ns
0
ns
Semiconductor Group
11-8
1997-10-01