C509-L_97 Datasheet, PDF (48/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
C509-L
Table 3-5
Contents of the SFRs, SFRs in numeric order of their addresses
Addr Register
Content Bit 7
after
Reset ¹⁾
Bit 6
Bit 5
Bit 4
Bit 3
80_H P0
FF_H
80_H DIR0
FF_H
81_H SP
07_H
82_H DPL
00_H
83_H DPH
00_H
84_H WDTL
00_H
85_H WDTH
00_H
86_H WDTREL 00_H
87_H PCON
00_H
88_H TCON
00_H
89_H TMOD
00_H
8A_H TL0
00_H
8B_H TL1
00_H
8C_H TH0
00_H
8D_H TH1
00_H
90_H P1
FF_H
.7
.6
.7
.6
.7
.6
.7
.6
.7
.6
.7
.6
.7
.6
WPSEL .6
SMOD PDS
TF1 TR1
GATE C/T
.7
.6
.7
.6
.7
.6
.7
.6
T2
CLK-
OUT
.5
.5
.5
.5
.5
.5
.5
.5
IDLS
TF0
M1
.5
.5
.5
.5
T2EX
.4
.4
.4
.4
.4
.4
.4
.4
SD
TR0
M0
.4
.4
.4
.4
INT2
.3
.3
.3
.3
.3
.3
.3
.3
GF1
IE1
GATE
.3
.3
.3
.3
INT6
90_H DIR1
FF_H
.7
.6
.5
.4
.3
91_H XPAGE 00_H
.7
.6
.5
.4
.3
92_H DPSEL
XXXX. –
–
–
–
–
X000_B
98_H S0CON 00_H
SM0 SM1 SM20 REN0 TB80
99_H S0BUF
XX_H
.7
.6
.5
.4
.3
9A_H IEN2
XX00. –
–
ECR ECS ECT
00X0_B
9B_H S1CON
0100. SM
0000_B
S1P SM21 REN1 TB81
9C_H S1BUF
XX_H
.7
.6
.5
.4
.3
9D_H S1RELL 00_H
.7
.6
.5
.4
.3
A0_H P2
FF_H
.7
.6
.5
.4
.3
A0_H DIR2
FF_H
.7
.6
.5
.4
.3
A1_H COMSETL 00_H
.7
.6
.5
.4
.3
1) X means that the value is indeterminate or the location is reserved.
2) SFRs with a comment in this column are mapped registers.
Shaded registers are bit-addressable special function registers.
Bit 2
.2
.2
.2
.2
.2
.2
.2
.2
GF0
IT1
C/T
.2
.2
.2
.2
INT5
.2
.2
.2
RB80
.2
ECMP
RB81
.2
.2
.2
.2
.2
Bit 1
.1
.1
.1
.1
.1
.1
.1
.1
PDE
IE0
M1
.1
.1
.1
.1
INT4
.1
.1
.1
TI0
.1
–
TI1
.1
.1
.1
.1
.1
Bit 0
.0
.0
.0
.0
.0
.0
.0
.0
IDLE
IT0
M0
.0
.0
.0
.0
INT3
.0
.0
.0
RI0
.0
ES1
RI1
.0
.0
.0
.0
.0
Mapped
by ²⁾
PDIR=0
PDIR=1
–
–
–
–
–
–
–
–
–
–
–
–
–
PDIR=0
PDIR=1
–
–
–
–
–
–
–
–
PDIR=0
PDIR=1
–
Semiconductor Group
3-23
1997-10-01