C509-L_97 Datasheet, PDF (190/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
6.6.4 A/D Conversion Timing
An A/D conversion is internally started by writing into the SFR ADDATL with dummy data. A write
to SFR ADDATL will start a new conversion even if a conversion is currently in progress. The
conversion begins with the next machine cycle, and the BSY flag in SFR ADCON0 will be set.
Basically, the A/D conversion procedure is divided into three parts:
– Sample phase (t_S), used for sampling the analog input voltage.
– Conversion phase (t_CO), used for the real A/D conversion.(includes calibration)
– Write result phase (t_WR), used for writing the conversion result into the ADDAT registers.
The total A/D conversion time is defined by t_ADCC which is the sum of the two phase times t_S and
t_CO. The duration of the three phases of an A/D conversion is specified by its specific timing
parameter as shown in figure 6-49.
Conversion Clock
Prescaler
ADCL1 ADCL0
0
0
0
1
1
0
1
1
Sample Clock
Prescaler
ADST1 ADST0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Sample
Time
t_S
8 x t_IN
16 x t_IN
32 x t_IN
64 x t_IN
16 x t_IN
32 x t_IN
64 x t_IN
128 x t_IN
32 x t_IN
64 x t_IN
128 x t_IN
256 x t_IN
64 x t_IN
128 x t_IN
256 x t_IN
512 x t_IN
Conversion
Time
t_CO
ConversionTime
t_ADCC
CPU Cycles
n Tim. Ref
40 x t_IN
48 x t_IN
8
a)
56 x t_IN
9
b)
72 x t_IN
12
a)
104 x t_IN 17
b)
80 x t_IN
96 x t_IN
16
a)
112 x t_IN 18
c)
144 x t_IN 24
a)
208 x t_IN 34
c)
160 x t_IN
192 x t_IN 32
a)
224 x t_IN 37
b)
288 x t_IN 48
a)
416 x t_IN 69
b)
320 x t_IN
384 x t_IN 64
a)
448 x t_IN 74
c)
576 x t_IN 96
a)
832 x t_IN 138 c)
Figure 6-49
A/D Conversion Timing
Semiconductor Group
6-112
1997-10-01