C509-L_97 Datasheet, PDF (194/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
6.6.5 Adjustment of the Sample Time
As already discussed, the maximum input clock f_ADC for the A/D converter is 2 MHz. This must be
taken into account when programming the A/D converter input clock prescalers. Additionally, the
C509-L allows to adapt the sample phase of an A/D conversion to the impedance of an analog input
source. This chapter gives some hints how an optimal adaption of the sample phase is achieved.
At the end of an A/D conversion (single conversion mode) the internal capacitor array is internally
precharged to a voltage level between V_AGND and V_AREF (approx. 2-3 V). When an A/D
conversion of an analog voltage U₀ is started, the voltage level at the analog input pin drops (or
raises) shortly to the precharge voltage level U_P and then raises (or drops) back to U₀ with a typical
RC load curve (see figure 6-51).
Figure 6-51
Typical Wavefoms at the Analog Inputs During the Sample Phase
The characteristics of the RC load curves as shown in figure 6-51 a) and b) is determined by the
input capacitance C_IN of the analog input pin, by the impedance R of the driving analog source, and
by the voltage difference between U₀ and U_P.
The external analog source needs to be strong enough (low impedance) to source the current for
loading the analog input capacitance. Depending on the accuracy or error requirements of an A/D
conversion, the limits for the input impedance of the analog source can be calculated using the
following formula :
R _MAX = - t _S / (C_IN • In (error) )
t _S : sample time
with error = 1 - ^u(t)
U₀
C_IN : analog input capacitance (typically 50 pF)
error : allowed deviation of U_IN from U₀ at the end of the sample time, given in %
Table 6-14 shows the resulting maximum values for R _MAX at f _OSC = 16 MHz and a maximum error
of 0.1% (1 or 2 LSB error allowed, additional to the specified total unadjusted error).
Semiconductor Group
6-116
1997-10-01