C509-L_97 Datasheet, PDF (231/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Power Saving Modes
C509-L
9.4 Software Power Down Mode
In the software power down mode, the on-chip oscillator is stopped. Therefore, all functions are
stopped, only the contents of the on-chip RAM and the SFR’s are held. The port pins controlled by
their port latches output the values that are held by their SFR’S. The port pins which serve the
alternate output functions show the values they had at the end of the last cycle of the instruction
which initiated the power down mode; when enabled, the clockout signal (P1.6/CLKOUT) will stop
at low level. ALE and PSEN are held at logic low level (see table 9-1).
lf the software power down mode is to be used, the pin PE/SWD must be held low. Entering the
software power down mode is done by two consecutive instructions immediately following each
other. The first instruction has to set the flag bit PDE (PCON.1) and must not set bit PDS (PCON.6).
The following instruction has to set the start bit PDS and must not set bit PDE. The hardware
ensures that a concurrent setting of both bits, PDE and PDS, will not initiate the power down mode.
Bit PDE and PDS will automatically be cleared after having been set and the value shown when
reading one of these bits is always zero (0). This double-instruction sequence is implemented to
minimize the chance of unintentional entering the software power down mode, which could possibly
“freeze” the chip’s activity in an undesired status.
Note that PCON is not a bit-addressable register, so the above mentioned sequence for entering
the software power down mode is composed of byte handling instructions.
The following instruction sequence may serve as an example:
ORL PCON,#00000010B
ORL PCON,#01000000B
;Set bit PDE, bit PDS must not be set
;Set bit PDS, bit PDE must not be set
The instruction that sets bit PDS is the last instruction executed before going into power down
mode. lf idle mode and software power down mode are invoked simultaneously, the software power
down mode takes precedence.
The only exit from software power down mode is a hardware reset. Reset will redefine all SFR’s, but
will not change the contents of the internal RAM.
In the software power down mode, V_CC can be reduced to minimize power consumption. Care must
be taken, however, to ensure that V_CC is not reduced before the software power down mode is
invoked, and that V_CC is restored to its normal operating level before software the power down mode
is terminated. The reset signal that terminates the software power down mode also frees the
oscillator. The reset should not be activated before V_CC is restored to its normal operating level and
must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on
reset).
Semiconductor Group
9-6
1997-10-01