C509-L_97 Datasheet, PDF (187/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
Bit
ADCL1
ADCL0
ADST1
ADST0
Function
A/D conversion clock prescaler selection
ADCL1 and ADCL0 select the prescaler ratio for the A/D conversion clock
f_ADC. Depending on the clock rate f_OSC of the C509-L. f_ADC must be selected
by the two prescaler bits ADCL1 and ADCL0 in a way that the resulting
frequency of the conversion clock f_ADC is less or equal 2 MHz.
The prescaler ratio is selected according the following table:
ADCL1
0
0
1
1
ADCL0
0
1
0
1
f _ADC Prescaler Ratio
divide by 4
divide by 8 (default after reset)
divide by 16
divide by 32
A/D sample clock prescaler selection
ADST1 and ADST0 select the prescaler ratio for the sample clock f_SC.
The prescaler ratio is selected according the following table:
ADST1
0
0
1
1
ADST0
0
1
0
1
f _SC Prescaler Ratio
divide by 2 (default after reset)
divide by 8
divide by 16
divide by 32
Note :Generally, before entering the power-down mode, an A/D conversion in progress must be
stopped. If a single A/D conversion is running, it must be terminated by polling the BSY bit or
waiting for the A/D conversion interrupt. In continuous conversion mode, bit ADM must be
cleared and the last A/D conversion must be terminated before entering the power-down
mode.
A single A/D conversion is started by writing to SFR ADDATL with dummy data. A continuous
conversion is started under the following conditions:
– By setting bit ADM during a running single A/D conversion
– By setting bit ADM when at least one A/D conversion has occurred after the last reset
operation.
– By writing ADDATL with dummy data after bit ADM has been set before (if no A/D conversion
has occurred after the last reset operation).
When bit ADM is reset by software in continuous conversion mode, the just running A/D conversion
is stopped after its end.
Semiconductor Group
6-109
1997-10-01