C509-L_97 Datasheet, PDF (102/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
6.2.2 Mode 0
Putting either timer/counter 0/1 into mode 0 configures it as an 8-bit timer/counter with a
divide-by-32 prescaler. Figure 6-13 shows the mode 0 operation.
In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1’s
to all 0’s, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an
interrupt (see section 8 for details about the interrupt structure). The counted input is enabled to the
timer when TR0 = 1 and either GATE = 0 or INT0 = 1 (setting GATE = 1 allows the timer to be
controlled by external input INT0, to facilitate pulse width measurements). TR0 is a control bit in the
special function register TCON; GATE is in TMOD.
The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0
are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers.
Mode 0 operation is the same for timer 0 as for timer 1. Substitute T0P1, T0P0, TR0, TF0, TH0,
TL0, T0 and INT0 with the corresponding timer 1 signals in figure 6-13.
Figure 6-13
Timer/Counter 0/1, Mode 0: 13 Bit Timer/Counter
Semiconductor Group
6-24
1997-10-01