C509-L_97 Datasheet, PDF (115/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
6.3.1.2.1 Gated Timer Mode
In gated timer function, the external input pin P1.7/T2 operates as a gate to the input of timer 2. lf
T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the counting procedure. This
will facilitate pulse width measurements. The external gate signal is sampled once every machine
cycle.
6.3.1.2.2 Event Counter Mode
In the event counter function, the timer 2 is incremented in response to a 1-to-0 transition at its
corresponding external input pin P1.7/T2. In this function, the external input is sampled every
machine cycle. When the sampled inputs show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the timer register in the cycle following the
one in which the transition was detected. Since it takes two machine cycles (12 oscillator periods)
to recognize a 1-to-0 transition, the maximum count rate is 1/12 of the oscillator frequency. There
are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is
sampled at least once before it changes, it must be held stable for at least one full machine cycle.
Note:
The prescaler must be turned off for proper counter operation of timer 2 (T2P1=T2P0=
T2PS1=T2PS=0).
In either case, no matter whether timer 2 is configured as timer, event counter, or gated timer, a
rolling-over of the count from all 1’s to all 0’s sets the timer overflow flag TF2 (bit 6 in SFR IRCON0,
interrupt request control) which can generate an interrupt.
lf TF2 is used to generate a timer overflow interrupt, the request flag must be cleared by the interrupt
service routine as it could be necessary to check whether it was the TF2 flag or the external reload
request flag EXF2 which requested the interrupt (for EXF2 see below). Both request flags cause the
program to branch to the same vector address.
6.3.1.2.3 Reload of Timer 2
The reload mode for timer 2 (see figure 6-19) is selected by bits T2R0 and T2R1 in SFR T2CON.
Two reload modes are selectable:
In mode 0, when timer 2 rolls over from all 1’s to all 0’s, it not only sets TF2 but also causes the
timer 2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software.
The reload will happen in the same machine cycle in which TF2 is set, thus overwriting the count
value 0000H.
In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the
corresponding input pin P1.5/T2EX. In addition, this transition will set flag EXF2, if bit EXEN2 in SFR
IEN1 is set.
lf the timer 2 interrupt is enabled, setting EXF2 will generate an interrupt. The external input pin
T2EX is sampled in every machine cycle. When the sampling shows a high in one cycle and a low
in the next cycle, a transition will be recognized. The reload of timer 2 registers will then take place
in the cycle following the one in which the transition was detected.
Semiconductor Group
6-37
1997-10-01