C509-L_97 Datasheet, PDF(44/290 Page) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

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C509-L_97 Datasheet, PDF (44/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

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Memory Organization

C509-L

Table 3-4

Special Function Registers - Functional Blocks

Block

Symbol Name

CPU

SFR

Mapping

ACC

B

DPH

DPL

DPSEL

PSW

SP

SYSCON1

Accumulator

B-Register

Data Pointer, High Byte

Data Pointer, Low Byte

Data Pointer Select Register

Program Status Word

Stack Pointer

System Control Register 1

SYSCON 2) System Control Register

Address

E0H 1)

F0H 1)

83H

82H

92H

D0H 1)

81H

B2H

B1H

Contents after

Reset

00H

00H

00H

00H

XXXXX000B 3)

00H

07H

00XXXEE0B3)6)

1010XX01B 3)

Interrupt

System

IEN0

CTCON 2)

CT1CON 2)

IEN1 2)

IEN2 2)

IEN3

IP0 2)

IP1 2)

IRCON0

IRCON1

IRCON2 4)

EICC1 4)

TCON 2)

T2CON 2)

Interrupt Enable Register 0

Compare Timer Control Register

Compare Timer 1 Control Register

Interrupt Enable Register 1

Interrupt Enable Register 2

Interrupt Enable Register 3

Interrupt Priority Register 0

Interrupt Priority Register 1

Interrupt Request Control Register 0

Interrupt Request Control Register 1

Interrupt Request Control Register 2

Interrupt Request Enable Register for CT1

Timer Control Register

Timer 2 Control Register

A8H1)

E1H

BCH

B8H 1)

9AH

BEH

A9H

B9H

C0H 1)

D1H

BFH

BFH

88H 1)

C8H 1)

00H

01000000B 3)

X1XX0000B 3)

00H

XX0000X0B 3)

XXXX00XXB 3)

00H

0X000000B 3)

00H

00H

00H

FFH

00H

00H

XRAM

XPAGE Page Address Register for XRAM

SYSCON 2) System Control Register

91H

B1H

00H

1010XX01B 3)

A/D

Converter

ADCON0

ADCON1

ADDATH

ADDATL

A/D Converter Control Register 0

A/D Converter Control Register 1

A/D Converter Data Register, High Byte

A/D Converter Data Register, Low Byte

D8H1)

DCH

D9H

DAH

00H

01000000B 3)

00H

00H

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) X means that the value is indeterminate or the location is reserved

4) Register is mapped by bit PDIR.

5) Register is mapped by bit RMAP.

6) âEâ means that the value of the bit is defined by the logic level at pin PRGEN at the rising edge of the RESET

or HWPD signals.

Semiconductor Group

3-19

1997-10-01

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