C509-L_97 Datasheet, PDF (35/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
C509-L
3.4.6 Special Function Register SYSCON1
There are five control bits located in SFR SYSCON1 (B2H) which control the code and data memory
organization of the C509-L. Two of these bits (PRGEN1 and SWAP) cannot be programmed as
normal bits but with a special software unlock sequence. The special software unlock sequence
was implemented to prevent unintentional changing of these bits and consists of consecutive
followed instructions which have to set two dedicated enable bits.
Special Function Register SYSCON1 (Address B2H)
Reset Value : 00XXXEE0B ¹⁾
MSB
Bit No. 7
6
5
B2H ESWC SWC –
LSB
4
3
2
1
0
EA1 EA0 PRGEN1 PRGEN0 SWAP SYSCON1
1) “E” means that the value of the bit is defined through the external logic level at
pin PRGEN at the rising edge of the external RESET or HWPD signals.
Bit
ESWC
SWC
–, EA1, EA0
PRGEN1
Function
Enable Switch Chipmode
When selecting the chipmode with the bits SWAP and PRGEN1, the ESWC bit has
to be set simultaneously as the first instruction in the special software unlock
sequence. The bit ESWC will be cleared by hardware after 2 instruction cycles.
Switch Chip Mode
The SWC bit has to be set as the second instruction in a special software unlock
sequence directly after having set bit ESWC. The new chipmode becomes active
after the second instruction cycle which follows the special software unlock
sequence. These two instruction cycles are used for initializing of the program
counter (LJMP instruction)
SWC is a write only bit. Reading SWC will always return a ‘0’.
Reserved bits; at read operations these bits are undefined; at write operations to
SYSCON1 these bits can be written with “0” or “1”.
Program Enable Bit 1
The PRGEN1 bit enables/disables the write accesses to an external FLASH
EPROM. The PRGEN1 bit contains the logic value of the external PRGEN pin
which is latched at the rising edge of the external RESET or HWPD signal. When
the logic low level appears at the PRGEN pin, the PRGEN1 bit will be cleared in the
next instruction cycle without the need of a special software unlock sequence.
PRGEN1 = 0: Write access (programming) of external FLASH EPROM is
disabled
PRGEN1 = 1: Write access (programming) of external FLASH EPROM is
enabled
Any changing the PRGEN1 bit without using a special software unlock sequence
with the ESWC and SWC bits will have no effect and the former selected status will
be kept.
Semiconductor Group
3-10
1997-10-01