C509-L_97 Datasheet, PDF (49/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
C509-L
Table 3-5
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
Addr Register
Content Bit 7
after
Reset ¹⁾
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mapped
by ²⁾
A2_H
A3_H
A4_H
A5_H
A6_H
A8_H
A9_H
AA_H
B0_H
B0_H
B1_H
B2_H
B4_H
B8_H
B9_H
BA_H
BB_H
BC_H
BE_H
BF_H
BF_H
C0_H
C1_H
COMSETH 00_H
COMCLRL 00_H
COMCLRH 00_H
SETMSK 00_H
CLRMSK 00_H
IEN0
00_H
IP0
00_H
S0RELL D9_H
P3
FF_H
DIR3
FF_H
SYSCON 1010.
XX01_B
SYSCON1 00XX.
3)
XEE0_B
PRSC
1101.
0101_B
IEN1
00_H
IP1
0X00.
0000_B
S0RELH XXXX.
XX11_B
S1RELH XXXX.
XX11_B
CT1CON X1XX.
0000_B
IEN3
XXXX.
00XX_B
IRCON2 00_H
EICC1
FF_H
IRCON0 00_H
CCEN
00_H
.7
.6
.5
.7
.6
.5
.7
.6
.5
.7
.6
.5
.7
.6
.5
EAL WDT ET2
OWDS WDTS .5
.7
.6
.5
RD WR T1
.7
.6
.5
CLKP PMOD 1
.4
.3
.4
.3
.4
.3
.4
.3
.4
.3
ES0 ET1
.4
.3
.4
.3
T0
INT1
.4
.3
RMAP –
.2
.2
.2
.2
.2
EX1
.2
.2
INT0
.2
–
.1
.0
–
.1
.0
–
.1
.0
–
.1
.0
–
.1
.0
–
ET0 EX0 –
.1
.0
–
.1
.0
–
TxD0 RxD0 PDIR=0
.1
.0
PDIR=1
XMAP1 XMAP0 –
ESWC SWC –
EA1 EA0 PRGEN1 PRGEN0 SWAP –
WDTP S0P T2P1 T2P0 T1P1 T1P0 T0P1 T0P0 –
EXEN2 SWDT EX6 EX5 EX4 EX3 EX2 EADC –
PDIR –
.5
.4
.3
.2
.1
.0
–
–
–
–
–
–
–
.1
.0
–
–
–
–
–
–
–
.1
.0
–
–
CT1P –
–
CT1F CLK12 CLK11 CLK10 –
–
–
–
–
ECT1 ECC1 –
–
–
ICC17 ICC16 ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 PDIR=0
EICC17 EICC16 EICC15 EICC14 EICC13 EICC12 EICC11 EICC10 PDIR=1
EXF2 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC –
COCAH COCAL3 COCAH COCAL2 COCAH COCAL1 COCAH COCAL0 –
3
2
1
0
1) X means that the value is indeterminate or the location is reserved.
2) SFRs with a comment in this column are mapped registers.
3) “E” means that the value of the bit is defined by the logic level at pin PRGEN at the rising edge of the RESET
or HWPD signals.
Shaded registers are bit-addressable special function registers.
Semiconductor Group
3-24
1997-10-01