C509-L_97 Datasheet, PDF (204/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Interrupt System
C509-L
The SFR IEN2 includes the enable bits for the compare match with compare register interrupts, the
compare timer overflow interrupt, and the serial interface 1 interrupt.
Special Function Register IEN2 (Address 9AH)
MSB
Bit No. 7
6
5
4
3
2
9AH
–
– ECR ECS ECT ECMP
Reset Value : XX0000X0B
LSB
1
0
– ES1 IEN2
Bit
–
ECR
ECS
ECT
ECMP
ES1
Function
Reserved bits for future use.
COMCLR register compare match interrupt enable
If ECR = 0, the COMCLR compare match interrupt is disabled.
COMSET register compare match interrupt enable
If ECS = 0, the COMSET compare match interrupt is disabled.
Enable compare timer interrupt enable
If ECT = 0, the compare timer overflow interrupt is disabled.
CM0-7 register compare match interrupt enable
If ECMP = 0, the CM0-7 compare match interrupt is disabled.
Serial Interface 1 interrupt enable
if ES1 = 0, the serial interrupt 1 is disabled.
Semiconductor Group
7-8
1997-10-01