C509-L_97 Datasheet, PDF (141/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
6.3.4.4.2 CMx Registers Assigned to the Timer 2
Any CMx register assigned to timer 2 as a time base operates in compare mode 1. In this case CMx
registers behave like any other compare register connected to timer 2 (e.g. the CRC or CCx
registers).
Since there are no dedicated interrupts for the CMx compare outputs, again a buffered compare
register structure is used to determine an exact 16-bit wide loading of the compare value: the
compare value is transferred to the actual compare latches at a write-to-CMLx instruction (low byte
of CMx). Thus, the CMx register is to be written in a fixed order, too: high byte first, low byte second.
lf the high byte may remain unchanged it is sufficient to load only the low byte. See figure 6-32,
block diagram of a CMx register connected to timer 2.
Figure 6-32
CMx-Register Assigned to Timer 2
Semiconductor Group
6-63
1997-10-01