C509-L_97 Datasheet, PDF (51/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
C509-L
Table 3-5
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
Addr Register
Content Bit 7
after
Reset ¹⁾
Bit 6
Bit 5
Bit 4
Bit 3
DA_H ADDATL 00_H
.7
.6
–
–
–
(LSB)
DB_H P7
–
.7
.6
.5
.4
.3
DC_H ADCON1 0100. ADCL1 ADCL0 ADST1 ADST0 MX3
0000_B
DD_H P8
–
–
.6
.5
.4
.3
DE_H CTRELL 00_H
.7
.6
.5
.4
.3
DE_H CT1RELL 00_H
.7
.6
.5
.4
.3
DF_H CTRELH 00_H
.7
.6
.5
.4
.3
DF_H CT1RELH 00_H
.7
.6
.5
.4
.3
E0_H ACC
00_H
.7
.6
.5
.4
.3
E1_H CTCON 0100. T2PS1 CTP ICR ICS CTF
0000_B
E2_H CML3
00_H
.7
.6
.5
.4
.3
E2_H CC1L3
00_H
.7
.6
.5
.4
.3
E3_H CMH3
00_H
.7
.6
.5
.4
.3
E3_H CC1H3
00_H
.7
.6
.5
.4
.3
E4_H CML4
00_H
.7
.6
.5
.4
.3
E4_H CC1L4
00_H
.7
.6
.5
.4
.3
E5_H CMH4
00_H
.7
.6
.5
.4
.3
E5_H CC1H4
00_H
.7
.6
.5
.4
.3
E6_H CML5
00_H
.7
.6
.5
.4
.3
E6_H CC1L5
00_H
.7
.6
.5
.4
.3
E7_H CMH5
00_H
.7
.6
.5
.4
.3
E7_H CC1H5
00_H
.7
.6
.5
.4
.3
E8_H P4
FF_H
CM7 CM6 CM5 CM4 CM3
E8_H DIR4
FF_H
.7
.6
.5
.4
.3
E9_H MD0
XX_H
.7
.6
.5
.4
.3
EA_H MD1
XX_H
.7
.6
.5
.4
.3
EB_H MD2
XX_H
.7
.6
.5
.4
.3
EC_H MD3
XX_H
.7
.6
.5
.4
.3
ED_H MD4
XX_H
.7
.6
.5
.4
.3
1) X means that the value is indeterminate or the location is reserved.
2) SFRs with a comment in this column are mapped registers.
Shaded registers are bit-addressable special function registers.
Bit 2 Bit 1
–
–
.2
MX2
.1
MX1
.2
.2
.2
.2
.2
.2
CLK2
.1
.1
.1
.1
.1
.1
CLK1
.2
.2
.2
.2
.2
.2
.2
.2
.2
.2
.2
.2
CM2
.2
.2
.2
.2
.2
.2
.1
.1
.1
.1
.1
.1
.1
.1
.1
.1
.1
.1
CM1
.1
.1
.1
.1
.1
.1
Bit 0
–
.0
MX0
.0
.0
.0
.0
.0
.0
CLK0
.0
.0
.0
.0
.0
.0
.0
.0
.0
.0
.0
.0
CM0
.0
.0
.0
.0
.0
.0
Mapped
by ²⁾
–
–
–
–
RMAP=0
RMAP=1
RMAP=0
RMAP=1
–
–
RMAP=0
RMAP=1
RMAP=0
RMAP=1
RMAP=0
RMAP=1
RMAP=0
RMAP=1
RMAP=0
RMAP=1
RMAP=0
RMAP=1
PDIR=0
PDIR=1
–
–
–
–
–
Semiconductor Group
3-26
1997-10-01