C509-L_97 Datasheet, PDF (42/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
C509-L
3.5 Special Function Registers
The registers, except the program counter and the four general purpose register banks, reside in
the special function register area. The special function register area consists of two portions: the
standard special function register area and two mapped special function register areas. Several
special function registers of the C509-L (CC10-17, CT1REL, CC1EN, CAFR) are located in the
mapped special function register area. For accessing the mapped special function register area, bit
RMAP in special function register SYSCON must be set. All other special function registers are
located in the standard special function register area.
For accessing the port direction registers, which define the input or output function of the
bidirectional port structure, bit PDIR in SFR IP1 is used. This port direction register access operates
similar to the mapped SFR accesses, but a double instruction sequence must be executed. The first
instruction has to set bit PDIR. Thereafter, the second instruction can read or write the direction
register. Further details about port direction selection see chapter 6.1.1.1.
The most right column of table 3-5 indicates if an SFR is accessed with a mapped procedure
controlled by either RMAP or PDIR.
Special Function Register SYSCON (Address B1H)
Special Function Register IP1 (Address B9H)
Reset Value : 1010XX01B
Reset Value : 0X000000B
Bit No. MSB
7
6
5
4
3
B1H ^{CLKP PMOD} 1 RMAP –
LSB
2
1
0
– XMAP1 XMAP0 _SYSCON
B9H PDIR –
.5
.4
.3
.2
.1
.0 IP1
Bit
RMAP
PDIR
The functions of the shaded bits are not described in this section.
Function
Special function register map bit
RMAP = 0: The access to the non-mapped (standard) special function
register area is enabled (reset value).
RMAP = 1: The access to the mapped special function register area is
enabled.
Direction register enable
PDIR = 0: Port register access is enabled (reset value).
PDIR = 1: Direction register is enabled.
PDIR will automatically be cleared after the second machine cycle (S2P2)
after having been set.
Semiconductor Group
3-17
1997-10-01