C509-L_97 Datasheet, PDF (233/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Power Saving Modes
C509-L
9.6 Hardware Power Down Mode
The C509-L has also a hardware power down mode. This mode can be initiated by an external
signal at the pin HWPD. This mode is referenced as hardware power down mode in opposite to the
program controlled software power down mode.
For a correct function of the hardware power down mode the oscillator watchdog unit including its
internal RC oscillator is needed. Therefore this unit must be enabled by pin OWE (OWE = high), if
the hardware power down mode shall be used. However, the control pin PE/SWD has no control
function for the hardware power down mode; it enables and disables only the use of all software
controlled power saving modes (slow down mode, idle mode, software power down mode).
The function of the hardware power down mode is as follows:
– The pin HWPD controls this mode. If it is on logic high level (inactive) the part is running in the
normal operating modes. If pin HWPD gets active (low level) the part enters the hardware
power down mode; as mentioned above this is independent of the state of pin PE/SWD.
HWPD is sampled once per machine cycle. If it is found active, the device starts a complete internal
reset sequence. This takes two machine cycles; all pins have their default reset states during this
time. This reset has exactly the same effects as a hardware reset; i.e.especially the watchdog timer
is stopped and its status flag WDTS is cleared. In this phase the power consumption is not yet
reduced. After completion of the internal reset both oscillators of the chip are disabled, the on-chip
oscillator as well as the oscillator watchdog's RC oscillator. At the same time the port pins and
several control lines enter a floating state as shown in table 9-2. In this state the power consumption
is reduced to the power down current IPD. Also the supply voltage can be reduced.
Table 9-2 also lists the voltages which may be applied at the pins during hardware power down
mode without affecting the low power consumption.
Semiconductor Group
9-8
1997-10-01