C509-L_97 Datasheet, PDF (80/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each
of the 8 digital I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop,
which will clock in a value from the internal bus in response to a “write-to-latch” signal from the CPU.
The Q output of the flip-flop is placed on the internal bus in response to a “read-latch” signal from
the CPU. The level of the port pin self is placed on the internal bus in response to a “read-pin” signal
from the CPU. Some instructions that read from a port activate the “read-port-latch” signal, while
others activate the “read-port-pin” signal.
Figure 6-1
Basic Structure of a Port Circuitry
Semiconductor Group
6-2
1997-10-01