C509-L_97 Datasheet, PDF(220/290 Page) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

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C509-L_97 Datasheet, PDF (220/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

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Fail Save Mechanisms

C509-L

8.1.1 Input Clock Selection

The input clock rate of the watchdog timer is derived from the system clock of the C509-L. There are

two prescalers which define the input clock rate. These prescalers are controlled by two bits in the

SFRs PRSC and WDTREL. Table 8-1 shows the resulting timeout periods at fOSC = 16 MHz.

Special Function Register PRSC (Address B4H)

Special Function Register WDTREL (Address 86H)

Reset Value : 11010101B

Reset Value : 00H

MSB

Bit No. 7

6

B4H WDTP S0P

5

T2P1

4

T2P0

3

T1P1

2

T1P2

1

T0P1

LSB

0

T0P0

PRSC

7

6

86H WPSEL

5

4

3

2

1

Watchdog timer reload value

0

WDTREL

The shaded bits are not used for the watchdog timer.

Bit

WDTP

WPSEL

WDTREL.6-0

Function

Prescaler select bits for the watchdog input clock

The two control bits WDTP and WPSEL deï¬ne the input clock frequency fIN of

the watchdog timer.

WDTP

0

0

1

1

WPSEL

0

1

0

1

Input clock

fIN = fOSC/12

fIN = fOSC/192

fIN = fOSC/24 (reset value)

fIN = fOSC/384

Watchdog timer reload value

Seven bit reload value for the high-byte of the watchdog timer. This value is

loaded to the WDT when a refresh is triggered by a consecutive setting of bits

WDT and SWDT.

Table 8-1

Watchdog Timer Timeout Periods at fOSC = 16 MHz

WDTREL

00H

7EH

7FH

fOSC/12

24.6 ms

381 Âµs

189 Âµs

Time-Out Periods

fOSC/24 fOSC/192

49.1 ms 393 ms

762 Âµs 6.10 ms

378 Âµs 3.02 ms

fOSC/384

786 ms

12.2 ms

6.05 ms

Comments

Maximum time period (default after reset)

(128 WDTL overï¬ows)

Two WDTL overï¬ows

Min. time period (One WDTL overï¬ow)

Semiconductor Group

8-2

1997-10-01

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