C509-L_97 Datasheet, PDF (24/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Fundamental Structure
C509-L
2.2 CPU Timing
A machine cycle consists of 6 states (6 oscillator periods). Each state is divided into a phase 1 half,
during OSC is high, and a phase 2 half, during which OSC is low. Thus, a machine cycle consists
of 6 oscillator periods, numbered S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each
state lasts for one oscillator period. Typically, arithmetic and logical operations take place during
phase 1 and internal register-to-register transfers take place during phase 2.
The diagrams in figure 2-2 show the fetch/execute timing related to the internal states and phases.
Since these internal clock signals are not user-accessible, the XTAL1 oscillator signals and the ALE
(address latch enable) signal are shown for external reference. ALE is normally activated twice
during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1.
Executing of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction
register. If it is a two-byte instruction, the second reading takes place during S4 of the same
machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would
be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In
any case, execution is completed at the end of S6P2.
Figures 2-2 a) and b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle
instruction.
Most C509-L instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the only
instructions that take more than two cycles to complete; they take four cycles. Normally two code
bytes are fetched from the program memory during every machine cycle. The only exception to this
is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that accesses
external data memory. During a MOVX, the two fetches in the second cycle are skipped while the
external data memory is being addressed and strobed. Figure 2-2 c) and d) show the timing for a
normal 1-byte, 2-cycle instruction and for a MOVX instruction.
Semiconductor Group
2-5
1997-10-01