C509-L_97 Datasheet, PDF (158/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
The first machine cycle of a shift left/right operation executes four shifts, while all following cycles
perform 6 shifts. Hence, a 31-bit shift takes 3 microseconds at 12 MHz. WIth a four bit shift operation
ther must be at least one machine cycle delay before the result registers MD0-3 can be accessed
as valid by the CPU.
Completion of both operations, normalize and shift, can also be controlled by the error flag
mechanism. The error flag is set if one of the relevant registers (MD0 through MD3) is accessed
before the previously commenced operation has been completed.
For proper operation of the error flag mechanism, it is necessary to take care that the right write or
read sequence to or from registers MD0 to MD3 (see table 6-11) is maintained.
Table 6-11
Programming a Shift or Normalize Operation
Operation
First write
Last write
First read
Last read
Normalize, Shift Left, Shift Right
MD0
MD1
MD2
MD3
ARCON
least significant byte
.
.
most significant byte
start of conversion
MD0
MD1
MD2
MD3
least significant byte
.
.
most significant byte
6.4.5 The Overflow Flag
An overflow flag is provided for some exceptions during MDU calculations. There are three cases
where flag MDOV ARCON.6 is set by hardware:
– Division by zero
– Multiplication with a result greater then 0000 FFFFH
(= auxiliary carry of the lower 16bit)
– Start of normalizing if the most significant bit of MD3 is set (MD3.7 = 1).
Any operation of the MDU which does not match the above conditions clears the overflow flag. Note
that the overflow flag is exclusively controlled by hardware. It cannot be written to.
6.4.6 The Error Flag
An error flag, bit MDEF in register ARCON (figure 6-56), is provided to indicate whether one of the
arithmetic operations of the MDU (multiplication, division, normalize, shift left/right) has been
restarted or interrupted by a new operation.
This can possibly happen e.g. when an interrupt service routine interrupts the writing or reading
sequence of the arithmetic operation in the main program and starts a new operation. Then the
contents of the corresponding registers are indeterminate (they would normally show the result of
the last operation executed).
Semiconductor Group
6-80
1997-10-01