C509-L_97 Datasheet, PDF (211/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Interrupt System
C509-L
The compare timer match interrupt occurs on a compare match of the CM0 to CM7 registers with
the compare timer when compare mode 1 is selected for the corresponding channel. There are 8
compare match interrupt flags available in SFR IRCON1 which are or-ed together for a single
interrupt request. Thus, a compare match interrupt service routine has to check which compare
match has requested the compare match interrupt. The ICMPx flags must be cleared by software.
Only if timer 2 is assigned to the CMx registers (compare mode 0), an ICMPx request flag is set by
every match in the compare channel. When the compare timer is assigned to the CMx registers
(compare mode 1), an ICMPx request flag will not be set by a compare match event.
Special Function Register IRCON1 (Address D1H)
Reset Value : 00H
MSB
LSB
Bit No. 7
6
5
4
3
2
1
0
D1H ICMP7 ICMP6 ICMP5 ICMP4 ICMP3 ICMP2 ICMP1 ICMP0
IRCON1
Bit
ICMP7 - 0
Function
Compare timer match with register CM7 - CM0 interrupt flags
ICMPx is set by hardware when a compare match of the compare timer with the
compare register CMx occurs but only if the compare function for CMx has been
enabled.
ICMPx must be cleared by software (CMSEL.x = 0 and CMEN.x = 1).
The compare timer 1 match interrupt occurs on a compare match of the CC10 to CC17 registers
with the compare timer 1 or (if selected) at a capture event at the pins CC10 to CC17. There are 8
compare match/capture interrupt flags available in SFR IRCON2 which are or-ed together for a
single interrupt request. Thus, a compare match/capture interrupt service routine has to check
which compare match/capture event has occurred. The ICC1x flags must be cleared by software.
Special Function Register IRCON2 (Address BFH)
Reset Value : 00H
MSB
LSB
Bit No. 7
6
5
4
3
2
1
0
BFH ICC17 ICC16 ICC15 ICC14 ICC13 ICC12 ICC11 ICC10
IRCON2
Bit
ICC17 - 10
Function
Compare timer 1 match with register CC17 - CC10 interrupt flags
ICC1x is set by hardware when a compare match of the compare timer 1 with the
compare register CC1x occurs but only if the compare function for CC1x has been
enabled.
ICC1x must be cleared by software.
Semiconductor Group
7-15
1997-10-01