C509-L_97 Datasheet, PDF (154/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
The arithmetic control register ARCON contains control flags and the shift counter of the MDU. It
triggers a shift or a normalize operation in register MD0 to MD3 when being written to.
Special Function Register ARCON (Address EFH)
Reset Value : 0XXXXXXXB
MSB
Bit No. 7
6
5
EFH MDEF MDOV SLR
4
SC.4
3
SC.3
2
SC.2
1
SC.1
LSB
0
SC.0
ARCON
Bit
MDEF
MDOV
SLR
SC.4 - SC.0
Function
Error flag
Indicates an improperly performed operation. MDEF is set by hardware
when an operation is retriggered by a write access to MDx before the first
operation has been completed. MDEF is automatically cleared after being
read.
Overflow flag
Exclusively controlled by hardware. MDOV is set by following events:
– division by zero
– multiplication with a result greater than FFFFH.
Shift direction bit
When set, shift right is performed. SLR = 0 selects shift left operation.
Shift counter bits
When preset with 00000B, normalizing is selected. After operation SC.0 to
SC.4 contain the number of normalizing shifts performed. When set with a
value ≠ 0, shift operation is started. The number of shifts performed is
determined by the count written to SC.0 to SC.4.
Semiconductor Group
6-76
1997-10-01