C509-L_97 Datasheet, PDF (234/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Power Saving Modes
C509-L
Table 9-2
Status of all Pins During Hardware Power Down Mode
Pins
Status
Voltage Range at Pin During
HW-Power Down
P0, P1, P2, P3, P4, Floating outputs / disabled input function V_SS ≤ V_IN ≤ V_CC
P5, P6, P7, P8, P9
EA
PE/SWD
active input
active input, pull-up resistor disabled
during HW power down
V_IN = V_CC or V_IN = V_SS
V_IN = V_CC or V_IN = V_SS
XTAL1
active output
pin may not be driven
XTAL2
PSEN/RDF, ALE
disabled input function
Floating outputs / disabled input function
(for test modes only)
V_SS ≤ V_IN ≤V_CC
V_SS ≤ V_IN ≤ V_CC
VAREF, VAGND
OWE
RESET
active supply pins
V_AGnd ≤ V_IN ≤ V_CC
active input; must be at high level for start- V_IN = V_CC
up after HW power down; pull up resistor or
disabled during HW-power down
(V_IN = V_SS)
active input; must be on high level if HW V_IN = V_CC
power down is used
R0
Floating output
V_SS ≤ V_IN ≤ V_CC
The power down state is maintained while pin HWPD is held active. If HWPD goes to high level
(inactive state) an automatic start up procedure is performed:
– First the pins leave their floating condition and enter their default reset state as they had
immediately before going to float state.
– Both oscillators are enabled (only if OWE = high). While the on-chip oscillator (with pins
XTAL1 and XTAL2) usually needs a longer time for start-up, if not externally driven (with
crystal approx. 1 ms), the oscillator watchdog's RC oscillator has a very short start-up time
(typ. less than 2 microseconds).
– Because the oscillator watchdog is active it detects a failure condition if the on-chip oscillator
hasn't yet started. Hence, the watchdog keeps the part in reset and supplies the internal clock
from the RC oscillator.
– Finally, when the on-chip oscillator has started, the oscillator watchdog releases the part from
reset after it performed a final internal reset sequence and switches the clock supply to the
on-chip oscillator. This is exactly the same procedure as when the oscillator watchdog detects
first a failure and then a recovering of the oscillator during normal operation. Therefore, also
the oscillator watchdog status flag is set after restart from hardware power down mode.
When automatic start of the watchdog was enabled (PE/SWD connected to V_CC), the
Watchdog Timer will start, too (with its default reload value for time-out period).
The SWD-Function of the PE/SWD pin is sampled only by a hardware reset. Therefore at least one
Power On Reset has to be performed.
Semiconductor Group
9-9
1997-10-01