C509-L_97 Datasheet, PDF (124/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
Contents
of a Timer
Register
Timer Count = FFFFH
Timer Count =
Compare Value
Timer Count = Reload Value
Interrupt can be generated
on overflow
Compare
Output
(P1.x/CCx)
Figure 6-22
Output Waveform of Compare Mode 0
MCT01846
Interrupt can be generated
on compare match
Modulation Range of a PWM Signal and Differences between the Two Timer/Compare
Register Configurations in the CCU
There are two timer/compare register configurations in the CCU which can operate in compare
mode 0 (either timer 2 with a CCx (CRC and CC1 to CC4) register or the compare timer with a CMx
register). They basically operate in the same way, but show some differences concerning their
modulation range when used for PWM.
Generally it can be said that for every PWM generation with n-bit wide compare registers there are
2ⁿ different settings for the duty cycle. Starting with a constant low level (0% duty cycle) as the first
setting, the maximum possible duty cycle then would be
(1 – 1/2ⁿ) x 100 %
This means that a variation of the duty cycle from 0% to real 100% can never be reached if the
compare register and timer register have the same length. There is always a spike which is as long
as the timer clock period.
In the C509-L there are two different modulation ranges for the above mentioned two timer/compare
register combinations. The difference is the location of the above spike within the timer period: at
the end of a timer period or at the beginning plus the end of a timer period. Please refer to the
description of the CCU relevant timer/register combination in section 6.3.4 for details.
Semiconductor Group
6-46
1997-10-01