C509-L_97 Datasheet, PDF (191/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
Sample Time t_S :
During this time the internal capacitor array is connected to the selected analog input channel and
is loaded with the analog voltage to be converted. The external analog source needs to be strong
enough to source the current to load the analog input capacitance during the load time. This causes
some restrictions for the impedance of the analog source. The analog voltage is internally fed to a
voltage comparator. With beginning of the sample phase the BSY bit in SFR ADCON0 is set.
Conversion Time t_CO :
During the conversion time the analog voltage is converted into a 10-bit digital value using the
successive approximation technique with a binary weighted capacitor network. During a conversion
alternating offset and linearity calibration cycles are executed (see also section 6.6.6). At the end
of the conversion phase the BSY bit is reset and the IADC bit in SFR ADCON0 is set indicating a
A/D converter interrupt condition.
Write Result Time t_WR :
At the result phase the conversion result is written into the ADDATH/ADDATL registers.
Figure 6-50 shows how an A/D conversion is embedded into the microcontroller cycle scheme
using the relation 6 x t _IN = 1 instruction cycle. It also shows the behaviour of the busy flag (BSY)
and the interrupt flag (IADC) during an A/D conversion.
Depending on the selected prescaler ratios (see figure 6-48), 3 different relationships between
machine cycles and A/D conversion are possible. These 3 relationships are referenced in the
rightmost column of the table in figure 6-49 as a), b), and c).
The single A/D conversion is started when SFR ADDATL is written with dummy data. This write
operation may take one or two machine cycles. In figure 6-50, the instruction MOV ADDATL,#0
starts the A/D conversion (machine cycle X-1 and X). The total A/D conversion (sample, conversion,
and calibration phase) is finished after the end of the n-th machine cycle. In the next machine cycle
n+1 the conversion result is written into the ADDAT registers and can be read in the same cycle by
an instruction (e.g. MOV A,ADDATL). If continuous conversion is selected (bit ADM set), the next
conversion is started with the beginning of the machine cycle which follows the writre result cycle.
The BSY bit is set at the beginning of the first A/D conversion machine cycle and reset at the
beginning of the write result cycle. If continuous conversion is selected, BSY is again set with the
beginning of the machine cycle which follows the write result cycle (n+1).
The interrupt flag IADC is set at the end of the A/D conversion. If the A/D converter interrupt is
enabled and the A/D converter interrupt is priorized to be serviced immediately, the first instruction
of the interrupt service routine will be executed in machine cycle n+4 or n+5. IADC must be reset
by software.
Semiconductor Group
6-113
1997-10-01