C509-L_97 Datasheet, PDF (136/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
Table 6-6
Configurations for Concurrent Compare Mode and Compare Mode 2 at Port 5
COCAH4 COCAL4 COCOEN1 COCOEN0 Function of CC4
0
0
0
0
Compare / Capture
1
disabled
1
1
0
1
0
0
Capture on
1
falling/rising edge at
pin
P1.4/INT2/CC4
1
0
0
0
Compare enable at
1
CC4; mode 0/1 is
selected by COMO
0
1
Compare mode 1 en-
abled at CC4; COMO
is automatically set
1
1
1
0
0
Capture on write
1
operation into register
CCL4
Function of Compare
Modes at P5
Disabled
Compare mode 2
selected, but only
interrupt generation
(ICR, ICS);
no output signals.at P5
Compare Mode 2
selected at P5
Disabled
Compare mode 2
selected, but only
interrupt generation
(ICR, ICS);
no output signals at P5
Disabled
Compare mode 2
selected, but only
interrupt generation
(ICR, ICS);
no output signals at P5
Concurrent compare
(mode 1) selected at
P5
Compare mode 2
selected at P5
Disabled
Compare mode 2
selected, but only
interrupt generation
(ICR, ICS);
no output signals at P5
Note : All other combinations of the 4 mode select bits are reserved and must not be used.
Semiconductor Group
6-58
1997-10-01