C509-L_97 Datasheet, PDF (214/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Interrupt System
C509-L
Table 7-2
Interrupts - Priority-within-Level
Interrupt Priority Bits
Group of Interrupt
Group
1
IP1.0 / IP0.0
2
IP1.1 / IP0.1
3
IP1.2 / IP0.0
4
IP1.3 / IP0.3
5
IP1.4 / IP0.4
6
IP1.5 / IP0.5
Interrupt Source Priority
High Priority
IE0
TF0
IE0
TF1
RI0 + TI0
TF2 + EXF2
RI1 + TI1
–
ICMP0-7
CTF
ICS
ICR
IADC
IEX2
IEX3
IEX4
IEX5
IEX6
Low Priority
–
–
ICC10-17
CTF1
–
–
Interrupt
Group
Priority
High
Low
Within one pair or triplet the leftmost interrupt is serviced first, then the second and third, when
available. The interrupt groups are serviced from top to bottom of the table. A low-priority interrupt
can itself be interrupted by a higher-priority interrupt, but not by another interrupt of the same or a
lower priority. An interrupt of the highest priority level cannot be interrupted by another interrupt
source.
If two or more requests of different priority levels are received simultaneously, the request of the
highest priority is serviced first. If requests of the same priority level are received simultaneously, an
internal polling sequence determines which request is to be serviced first. Thus, within each priority
level there is a second priority structure which is illustrated in table 7-2.
The “priority-within-level” structure is only used to resolve simultaneous requests of the same
priority level.
Semiconductor Group
7-18
1997-10-01