C509-L_97 Datasheet, PDF (38/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
C509-L
3.4.7.1 Special Software Unlock Sequence
The bits ESWC and SWC in SFR SYSCON1 are implemented in a way to prevent unintentional
changing of the bits SWAP or PRGEN1. Any changing the bits SWAP or PRGEN1 without using
the ESWC and SWC bits in a special software unlock sequence will have no effect and the above
bits will get back their old values two instruction cycles after being changed.
The following programming steps must be executed at the ESWC/SWC unlock sequence:
1.) First instruction:
Changing the value of the bits SWAP or PRGEN1 with one or more consecutive instructions
simultaneously with setting of bit ESWC:
ANL SYSCON1, #11111X1YB
ORL SYSCON1, #10000X0YB
; clearing of bits PRGEN1 (X=0) and/or SWAP (Y=0)
; setting of ESWC bit with setting of PRGEN1 or SWAP
; e.g. clearing of the SWAP bit:
ANL SYSCON1,#11111110B
ORL SYSCON1,#10000000B
or:
ORL SYSCON1, #10000X0YB
; setting of the bits PRGEN1 (X=1) and/or SWAP (Y=1) and
; setting the ESWC bit simultaneously
; e.g. setting of the SWAP bit:
ORL SYSCON1,#10000001B
2.) Second instruction:
Setting of bit SWC immediately after 1.) with
ORL SYSCON1, #40H
;
The new chipmode becomes active two instruction cycles after the instruction which sets the bit
SWC (see 2.). These two instruction cycle delay should normally be used for initialization of the
program counter to the 16 bit start-address of the new code memory resource, e.g. with:
LJMP 0XXXXH
; XXXX = 16-bit hex address in new code memory
If the code memory resource is not changed by the new chipmode there is no need of a new
initialization of the program counter. However the new Chipmode becomes active two instruction
cycles after 2.).
The special software unlock instruction sequence cannot be interrupted by an interrupt request. Any
write or read operation to SFR SYSCON1 will block the interrupt generation for the first cycle of the
directly following instruction.Therefore, the response time of an interrupt request may be
additionally delayed from minimal five instruction cycles up to eight instruction cycles: four or six
instruction cycles for setting ESWC and SWC (depends on the used instructions) and one or two
instruction cycles depending on the instruction used in 3.). When using a one cycle instruction in 3.)
an enabled interrupt may be performed and the interrupt vector address may reside in a “new” code
memory resource due to the new selected Chipmode.
The bits SWAP and PRGEN1 are built up by three shadow latches each. Unintentional changing of
one of this three latches (e.g. by RFI) will have no effect and the former value will be restored in the
next instruction cycle.
Semiconductor Group
3-13
1997-10-01