C509-L_97 Datasheet, PDF (123/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
6.3.3.1 Compare Mode 0
In mode 0, upon matching the timer and compare register contents, the output signal changes from
low to high. lt goes back to a low level on timer overflow. As long as compare mode 0 is enabled,
the appropriate output pin is controlled by the timer circuit only, and not by the user. Writing to the
port will have no effect. Figure 6-21 shows a functional diagram of a port circuit when used in
compare mode 0. The port latch is directly controlled by the timer overflow and compare match
signals. The input line from the internal bus and the write-to-latch line of the port latch are
disconnected when compare mode 0 is enabled.
Compare mode 0 is ideal for generating pulse width modulated output signals, which in turn can be
used for digital-to-analog conversion via a filter network or by the controlled device itself (e.g. the
inductance of a DC or AC motor). Compare mode 0 may also be used for providing output clocks
with initially defined period and duty cycle. This is the mode which needs the least CPU time. Once
set up, the output goes on oscillating without any CPU intervention. Figure 6-22 illustrates the
function of compare mode 0.
Port Circuit
Compare Register
Circuit
Compare Reg.
16 Bit
Comparator
16 Bit
Timer Register
Timer Circuit
Compare
Match
Timer
Overflow
Internal
Bus
Write to
Latch
Read Latch
V_CC
S
D _Port ^Q
Port
Pin
Latch
CLK
Q
R
Read Pin
MCS02661
Figure 6-21
Port Latch in Compare Mode 0
Figure 6-22 shows a typical output signal waveform which is generated when compare mode 0 is
selected.
Semiconductor Group
6-45
1997-10-01