C509-L_97 Datasheet, PDF (161/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
In all four modes, transmission is initiated by any instruction that uses S0BUF as a destination
register. Reception is initiated in mode 0 by the condition RI0 = 0 and REN0 = 1. Reception is
initiated in the other modes by the incoming start bit if REN0 = 1. The serial interfaces also provide
interrupt requests when a transmission or a reception of a frame has completed. The corresponding
interrupt request flags for serial interface 0 are TI0 or RI0, resp. See chapter 7 of this user manual
for more details about the interrupt structure. The interrupt request flags TI0 and RI0 can also be
used for polling the serial interface 0 if the serial interrupt is not to be used (i.e. serial interrupt 0 not
enabled).
The control and status bits of the serial interface 0 are located in special function register S0CON.
S0BUF is the receive and transmit buffer of serial interface 0. Writing to S0BUF loads the transmit
register and initiates transmission. Reading out S0BUF accesses a physically separate receive
register.
6.5.1.2 Multiprocessor Communication Feature
Modes 2 and 3 of the serial interface 0 have a special provision for multi-processor communication.
In these modes, 9 data bits are received. The 9th bit goes into RB80. Then a stop bit follows. The
port can be programmed such that when the stop bit is received, the serial port 0 interrupt will be
activated (i.e. the request flag RI0 is set) only if RB80 = 1. This feature is enabled by setting bit
SM20 in S0CON. A way to use this feature in multiprocessor communications is as follows.
lf the master processor wants to transmit a block of data to one of the several slaves, it first sends
out an address byte which identifies the target slave. An address byte differs from a data byte in
that the 9th bit is 1 in an address byte and 0 in a data byte. With SM20 = 1, no slave will be
interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave
can examine the received byte and see if it is being addressed. The addressed slave will clear its
SM20 bit and prepare to receive the data bytes that will be coming. After having received a complete
message, the slave sets SM20 again. The slaves that were not addressed leave their SM20 set and
go on about their business, ignoring the incoming data bytes.
SM20 has no effect in mode 0. In mode 1 SM20 can be used to check the validity of the stop bit. lf
SM20 = 1 in mode 1, the receive interrupt will not be activated unless a valid stop bit is received.
Semiconductor Group
6-83
1997-10-01