C509-L_97 Datasheet, PDF (75/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Reset / System Clock
C509-L
5.4 Reset Output Pin (RO)
As mentioned before the C509-L internally synchronizes an external reset signal at pin RESET in
order to perform a reset procedure. Additionally, the C509-L provides several "fail-save"
mechanisms, e.g. watchdog timer and oscillator watchdog, which can internally generate a reset,
too. Thus, it is often important to inform also the peripherals external to the chip that a reset is being
performed and that the controller will soon start its program again.
For that purpose, the C509-L has a pin dedicated to output the internal reset request. This reset
output (RO) shows the internal (and already synchronized) reset signal requested by any of the
three possible sources in the C509-L: external hardware reset, watchdog timer reset, or oscillator
watchdog reset. The duration of the active low signal of the reset output depends on the source
which requests it. In the case of the external hardware reset it is the synchronized external reset
signal at pin RESET. In the case of a watchdog timer reset or oscillator watchdog reset the RO
signal takes at least two machine cycles, which is the minimal duration for a reset request allowed.
For details - how the reset requests are OR-ed together and how long they last - see also chapter
8 "Fail-Save Mechanisms" .
5.5 Oscillator and Clock Circuit
XTAL1 and XTAL2 are the output and input of a single-stage on-chip inverter which can be
configured with off-chip components as a Pierce oscillator. The oscillator, in any case, drives the
internal clock generator. The clock generator provides the internal clock signals to the chip at half
the oscillator frequency. These signals define the internal phases, states and machine cycles.
Figure 5-4 shows the recommended oscillator circuit.
Figure 5-4
Recommended Oscillator Circuit
Semiconductor Group
5-6
1997-10-01