C509-L_97 Datasheet, PDF (189/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
6.6.3 A/D Converter Clock Selection
The ADC uses basically three clock signals for operation: the input clock f_IN (=1/t_IN), the conversion
clock f_ADC (=1/t_ADC) and the sample clock f_SC (=1/t_SC). All clock signals are derived from the
C509-L system clock f_OSC which is applied at the XTAL pins. The input clock f_IN is equal to f_OSC
while the conversion clock and the sample clock must be adapted. The conversion clock is limited
to a maximum frequency of 2 MHz. Therefore, the conversion clock prescaler must be programmed
to a value which assures that the conversion clock does not exceed 2 MHz. The prescaler ratio of
the conversion clock is selected by the bits ADCL1 and ADCL0 of SFR ADCON1. The sample clock
f_SC can be adapted to the requirements of the impedance of A/D converter input signal sources.
The prescaler ratio of the sample clock is selected by the bits ADST1 and ADST0 of SFR ADCON1.
Figure 6-48 shows the configuration of the two A/D converter prescalers. The table in figure 6-48
defines the divider ratio for the conversion and sample clock of each combination of the prescaler
bits.
Conversion Clock f_ADC
ADCL1 ADCL0 f_ADC
0
0
f_IN / 4
0
1
f_IN / 8
1
0
f_IN / 16
1
1
f_IN / 32
Sample Clock f_SC
ADST1 ADST0 ADST1 ADST0 ADST1 ADST0 ADST1 ADST0
0
0
0
1
1
0
1
1
f_IN / 8
f_IN / 16
f_IN / 32
f_IN / 64
f_IN / 16
f_IN / 32
f_IN / 64
f_IN / 128
f_IN / 32
f_IN / 64
f_IN / 128
f_IN / 256
f_IN / 64
f_IN / 128
f_IN / 256
f_IN / 512
Figure 6-48
A/D Converter Clock Selection
The duration of an A/D conversion is a multiple of the period of the f_IN clock signal. The timing of
the A/D conversion and the calculation of an A/D conversion time are shown in the next section.
Semiconductor Group
6-111
1997-10-01