C509-L_97 Datasheet, PDF (50/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
C509-L
Table 3-5
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
Addr Register
Content Bit 7
after
Reset ¹⁾
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mapped
by ²⁾
C2_H CCL1
00_H
C3_H CCH1
00_H
C4_H CCL2
00_H
C5_H CCH2
00_H
C6_H CCL3
00_H
C7_H CCH3
00_H
C8_H T2CON 00_H
C9_H CC4EN 00_H
.7
.6
.5
.4
.3
.2
.1
.0
–
.7
.6
.5
.4
.3
.2
.1
.0
–
.7
.6
.5
.4
.3
.2
.1
.0
–
.7
.6
.5
.4
.3
.2
.1
.0
–
.7
.6
.5
.4
.3
.2
.1
.0
–
.7
.6
.5
.4
.3
.2
.1
.0
–
T2PS I3FR I2FR T2R1 T2R0 T2CM T2I1 T2I0 –
COCO COCO COCO COCO COCO COCAH COCAL COMO –
EN1
N2
N1
N0
EN0 4
4
CA_H CRCL
00_H
CB_H CRCH
00_H
CC_H TL2
00_H
CD_H TH2
00_H
CE_H CCL4
00_H
CF_H CCH4
00_H
D0_H PSW
00_H
D1_H IRCON1 00_H
D2_H CML0
00_H
D2_H CC1L0
00_H
D3_H CMH0
00_H
D3_H CC1H0
00_H
D4_H CML1
00_H
D4_H CC1L1
00_H
D5_H CMH1
00_H
D5_H CC1H1
00_H
D6_H CML2
00_H
D6_H CC1L2
00_H
D7_H CMH2
00_H
D7_H CC1H2
00_H
D8_H ADCON0 00_H
D9_H ADDATH 00_H
.7
.6
.5
.4
.3
.2
.1
.0
–
.7
.6
.5
.4
.3
.2
.1
.0
–
.7
.6
.5
.4
.3
.2
.1
.0
–
.7
.6
.5
.4
.3
.2
.1
.0
–
.7
.6
.5
.4
.3
.2
.1
.0
–
.7
.6
.5
.4
.3
.2
.1
.0
–
CY
AC
F0
RS1 RS0 OV F1
P
–
ICMP7 ICMP6 ICMP5 ICMP4 ICMP3 ICMP2 ICMP1 ICMP0 –
.7
.6
.5
.4
.3
.2
.1
.0
RMAP=0
.7
.6
.5
.4
.3
.2
.1
.0
RMAP=1
.7
.6
.5
.4
.3
.2
.1
.0
RMAP=0
.7
.6
.5
.4
.3
.2
.1
.0
RMAP=1
.7
.6
.5
.4
.3
.2
.1
.0
RMAP=0
.7
.6
.5
.4
.3
.2
.1
.0
RMAP=1
.7
.6
.5
.4
.3
.2
.1
.0
RMAP=0
.7
.6
.5
.4
.3
.2
.1
.0
RMAP=1
.7
.6
.5
.4
.3
.2
.1
.0
RMAP=0
.7
.6
.5
.4
.3
.2
.1
.0
RMAP=1
.7
.6
.5
.4
.3
.2
.1
.0
RMAP=0
.7
.6
.5
.4
.3
.2
.1
.0
RMAP=1
BD
CLK ADEX BSY ADM MX2 MX1 MX0 –
.7
.6
.5
.4
.3
.2
.1
.0
–
(MSB)
1) X means that the value is indeterminate or the location is reserved.
2) SFRs with a comment in this column are mapped registers.
Shaded registers are bit-addressable special function registers.
Semiconductor Group
3-25
1997-10-01